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800 ma ultralow noise, high psrr, rf linear regulator data sheet ADM7151 features input voltage range: 4.5 v to 16 v maximum output current: 800 ma adjustable output from 1.5 v to 5.1 v low n oise 1.0 v rms total integrated noise from 100 hz to 100 k hz 1.6 v rms total integrated noise from 10 hz to 100 khz noise spectral dens ity : 1.7 nvhz from 10 khz to 1 mhz power supply rejection ratio (psrr) at 400 ma l oad >90 db from 1 khz to 100 khz, v out = 5 v >60 db at 1 mhz, v out = 5 v dropout voltage: 0.6 v at v out = 5 v, 800 ma load initial voltage accuracy: 1% voltage accuracy over line, load and temperature: 2% quiescent c urrent ( i gnd ) : 4. 3 ma at no load low shutdown current: 0.1 a stable with a 10 f ceramic output capacitor 8 - lead lfcsp package and 8 - lead soic package applications regulated power noise sensitive applications rf m ixe rs, phase - locked loops (plls), voltage - controlled oscillators (vcos), and plls with i ntegrated vcos clock distribution circuits ultrasound and other imaging applications high speed rf transceivers high speed, 16 - bit or greater adcs communications and i nfr astructure cable digital - to - analog converter (dac) drivers typical application circuit vout ref ref_sense gnd vin en byp vreg v byp v reg ADM7151-04 c reg 10f c byp 1f c ref 1f v out = 1.5v (r1 + r2)/r2 1k < r2 < 200k c in 10f c out 10f off on v in = 6.2v v out = 5.0v r1 r2 1 1480-001 figure 1. ADM7151 - 04 with v out = 5 v general description the a dm7151 is a low dropout (ldo) linear regulator that operates from 4.5 v to 16 v and provides up to 800 ma of output current. using an advanced proprietary architecture, it provide s high power supply rejection ( >90 db from 1 khz to 1 mhz ) , ultra low noise ( 1.7 nvhz from 10 khz to 1 mhz ) , and excellent line and load transient response with a 10 f ceramic output capacitor. the output voltage can be set to any voltage between 1.5 v and 5.1 v with two resistors. the ADM7151 is avail able in two models that optimize power dissipation and psrr performance as a function of input and output voltage . s ee table 6 and table 7 for selection guide s. the ADM7151 regulator output noise is 1. 0 v rms from 100 hz to 100 k hz , and the noise spectral density is 1.7 nv/hz from 10 khz to 1 mhz . the ADM7151 is available in 8 - lead, 3 mm 3 mm lfcsp and 8 - lead soic packages, making it not only a very compact solution, but also providing excellent thermal per formance for applications requiring up to 800 ma of output current in a small, low profile footprint . 100k 1 10 100 1k 10k 0.1 1 10 100 1k 10k 100k 1m noise spectral density (nv/hz) frequency (hz) c byp = 1f c byp = 10f c byp = 100f c byp = 1mf 11480-002 figure 2 . noise spectral density (nsd) vs . frequency for various c byp rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and r egistered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
ADM7151 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 15 applic ations information .............................................................. 16 model selection .......................................................................... 16 capacitor selection .................................................................... 16 enable (en) and undervoltage lockout (uvlo) ................. 18 start - up time ............................................................................. 19 ref, byp, and vreg pins ......................................................... 19 current - limit and thermal overload protection ................. 19 thermal considerations ............................................................ 19 printed circuit board layo ut considerations ........................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 9/13 revision 0 : initial version rev. 0 | page 2 of 24
data sheet ADM7151 specifications v in = 4.5 v, v out = 1.5 v, v ref = v ref_s ense (unity gain), v en = v in , i out = 10 ma, c in = c out = c reg = 10 f, c ref = c byp = 1 f. t a = 25c for typical specifications. t j = ?40c to +125c for minimum/maximum specificatio ns, unless otherwise noted. table 1 . parameter symbol test conditions /comments min typ max unit input voltage range v in 4.5 16 v operating supply current i gnd i out = 0 a 4.3 7 .0 ma i out = 800 ma 8.6 1 2 ma shutdown curre nt i in - sd v en = gnd 0.1 3 a output noise out noise 10 hz to 100 khz, i ndependent of output voltage 1.6 v rms 100 hz to 100 khz, i ndependent of output voltage 1.0 v rms noise spectral density nsd 10 khz to 1 mhz, i ndependent of output voltage 1 .7 nv/hz power supply rejection ratio psrr ADM7151 - 04 1 k hz to 100 k hz, v in = 6.2 v, v out = 5 v at 800 ma 84 db 1 mhz, v in = 6.2 v, v out = 5 v at 800 ma 53 db 1 k hz to 100 k hz, v in = 6.2 v, v out = 5 v at 400 ma 94 db 1 mhz, v in = 6.2 v, v out = 5 v at 400 ma 67 db ADM7151 - 02 1 k hz to 100 k hz, v in = 5.2 v, v out = 4 v at 800 ma 91 db 1 mhz, v in = 5.2 v , v out = 4 v at 800 ma 50 db 1 k hz to 100 k hz, v in = 5.2 v, v out = 4 v at 400 ma 94 db 1 mhz, v in = 5.2 v, v out = 4 v at 400 ma 58 db v out voltage accuracy v out = v ref voltage accuracy v out i out = 10 ma ? 1 +1 % 1 ma < i out < 800 ma , over line, load and temperature ? 2 +2 % v out regulation line regulation v out / v in v in = 4.5 v to 16 v ? 0.01 +0.01 %/v load regulation 1 v out / i out i out = 1 ma to 800 ma 0.5 1.0 %/a current - limit threshold i li mit v ref current limit threshold 20 ma v out current limit threshold 2 1.0 1.3 1.6 a dropout voltage 3 v dropout i out = 400 ma, v out = 5 v 0.30 0.60 v i out = 800 ma, v out = 5 v 0.60 1.20 v pull - down resistance v out pull - down resistan ce v out - pull v en = 0 v, v out = 1 v 600 v reg pull - down resistance v reg - pull v en = 0 v, v reg = 1 v 34 k v ref pull - down resistance v ref - pull v en = 0 v, v ref = 1 v 800 v byp pull - down resistance v byp - pull v en = 0 v, v byp = 1 v 500 start - up time 4 v out = 5 v v out start - up t ime t start - up 2.8 ms v reg start - up time t reg - start - up 1.0 ms v ref start - up time t ref - start - up 1.8 ms thermal shutdown thermal shutdown threshold ts sd t j rising 155 c thermal shutdown hysteresis ts sd - hys 15 c undervoltage thresholds input voltage rising uvlo rise t j = ?40c to +125c 4.49 v input voltage falling uvlo fal l t j = ?40c to +125c 3.85 v hysteresis uvlo hys 240 mv rev. 0 | page 3 of 24
ADM7151 data sheet parameter symbol test conditions /comments min typ max unit v reg 5 undervoltage thresholds v reg ris e vreguvlo rise t j = ?40 c to +125c 3.1 v v reg fall vreguvlo fal l t j = ?40c to +125c 2 .55 v hysteresis vreguvlo hys 210 mv en input 4.5 v v in 16 v en input logic high en high 3.2 v en input logic low en low 0.8 v en input logic hysteresis en hys v in = 5 v 225 mv en input leakage current i en - lkg v en = v in or gnd 0.1 1.0 a 1 based on an end - point calculation using 1 m a and 800 ma loads. see figure 6 and figure 13 for typical load re gulation performance for loads less than 1 m a . 2 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 5 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 v, or 4.5 v. 3 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to achieve the nominal output voltage. dropout applies only for output voltages above 4.5 v. 4 start - up time is defined as the time between the rising edge of v en to v out , v reg , or v ref being at 90% of its nominal value. 5 the output voltage is turned off until the v reg uvlo rise threshold is crossed. the v reg output is turned off until the input voltage uvlo rising threshold is crossed. input and output cap acitor, recommended specifications table 2 . parameter symbol test conditions/comments min typ max unit capacitance t a = ?40c to +125c minimum input 1 c in 7.0 f minimum regulator 1 c reg 7.0 f minimum output 1 c out 7.0 f minimum bypass c byp 0.1 f minimum reference c ref 0.7 f capacitor equivalent series resistance (esr) r esr t a = ?40c to +125c c r eg , c out , c in , c ref 0.001 0.2 c byp 0.001 2.0 1 the minimum input, regulator , and output capacitance must be greater than 7.0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7 r and x5r type capacito rs are recommended; however, y5v and z5u capacitors are not recommended for use with any ldo. rev. 0 | page 4 of 24
data sheet ADM7151 absolute maximum rat ings table 3 . parameter rating vin to gnd ? 0.3 v to +18 v vreg to gnd ? 0.3 v to vin, or +6 v (whichever is less) vout to gnd ? 0.3 v to vreg, or +6 v (whichever is less) vout to byp 0.3 v en to gnd ? 0.3 v to18 v byp to gnd ? 0.3 v to vreg, or +6 v (whichever is less) ref to gnd ? 0.3 v to vreg, or +6 v (whichever is less) ref_sense to gnd ? 0.3 v to +6 v storage temperature range ? 65c to +150c junction temperature 150c operating ambient temperature range C 40c to +125c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functi onal operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the ADM7151 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low printed circuit board ( pcb ) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), a nd the junction to ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction to ambient thermal resistance ( ja ) of the package is b ased on modeling and calculation using a 4 - layer board. the junction to ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in. 3 in. circuit board. see jesd51 - 7 and jesd51 - 9 for detailed information on the board construct ion. jb is the junction to board thermal characterization parameter with units of c/w. jb of the package is based on modeling and the calculation using a 4 - layer board. the jesd51 - 12, guidelines for reporting and using electronic package thermal informa tion , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance ( jb ) . therefore, jb thermal paths in clude convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) usi ng the formula t j = t b + ( p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja , jc , and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packa ges . table 4 . thermal resistance package type ja jc jb unit 8 - lead lfcsp 36.7 23.5 13.3 c/w 8 - lead soic 36.9 27.1 18.6 c/w esd caution rev. 0 | page 5 of 24
ADM7151 data sheet pin configurations a nd function descript ions 3 by p 4 gnd 1 vreg 2 vout 6 ref 5 ref_sense 8 vin 7 en ADM7151 top view (not to scale) 1 1480-003 notes 1. exposed pad on the bottom of the package. exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation. figure 3. 8 - lead lfcsp pin configuration ADM7151 top view (not to scale) vref 1 vout 2 by p 3 gnd 4 vin 8 en 7 ref 6 ref_sense 5 1 1480-004 notes 1. exposed pad on the bottom of the package. exposed pad enhances thermal performance and is electrically connected to gnd inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation. figure 4. 8 - lead soic pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 vreg regulated input supply to ldo amplifier. bypass v reg to gnd with a 10 f or greater capacitor. do not connect a load to ground . 2 vout regulated output voltage. bypass vout to gnd with a 10 f or greater capacitor. 3 byp low noise bypass capacitor. connect a 1 f capacitor to gnd to reduce noise. do no t connect a load to ground . 4 gnd ground connection. 5 ref_sense external resistor divider u sed to s et the output voltage . v out = v ref (r1 + r2)/ r 2 , where v ref = 1.5 v . 6 ref low noise reference voltage output. bypass ref to gnd with a 1 f capacitor. short ref_sense to ref for fixed output voltages. do not connect a load to ground . 7 en enable. drive en high to turn on the regulator and drive en low to turn off the regulator. for automatic startup, connect en to vin. 8 vin regulator input supply. b ypass vin to gnd with a 10 f or greater capacitor. ep ep exposed p ad on the b ottom of the p ackage. exposed pad enhances thermal performance and is electrically connected to gnd inside the package. c onnect the exposed pad to the ground plane on the board to ensure proper operation . rev. 0 | page 6 of 24
data sheet ADM7151 typical performance characteristics v in = v out + 1.2 v or v in = 4.5 v , whichever is greater, en = v in , i out = 10 ma, c in = c out = c reg = 10 f, c ref = c byp = 1 f, t a = 25c, unless otherwise noted. 4.04 3.96 3.97 3.98 3.99 4.00 4.01 4.02 4.03 ?40 ?5 25 85 125 v out (v) junction temperature (c) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1480-005 figure 5 . output voltage (v out ) vs. junction temperature (t j ), ADM7151 - 02, v out = 4 v 4.04 3.96 3.97 3.98 3.99 4.00 4.01 4.02 4.03 1 10 100 1000 v out (v) i load (ma) 1 1480-006 figure 6 . output voltage (v out ) vs. load current (i load ), ADM7151 - 02, v out = 4 v 4.04 3.96 3.97 3.98 3.99 4.00 4.01 4.02 4.03 5 16 15 14 13 12 11 10 9 8 7 6 v out (v) v in (v) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1480-007 figure 7. output voltage (v out ) vs. input voltage (v in ), ADM7151 - 02, v out = 4 v ?40 ?5 25 85 125 ground current (ma) junction temperature (c) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 10 0 1 2 3 4 5 6 7 8 9 1 1480-008 figure 8 . ground current vs. junction temperature (t j ), ADM7151 - 02, v out = 4 v 10 0 1 2 3 4 5 6 7 8 9 1 10 100 1000 ground current (ma) i load (ma) 1 1480-009 figure 9 . ground current vs. load current (i load ), ADM7151 - 02, v out = 4 v 10 0 1 2 3 4 5 6 7 8 9 5 16 15 14 13 12 11 10 9 8 7 6 ground current (ma) v in (v) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1480-010 figure 10 . ground current vs. input voltage (v in ), ADM7151 - 02, v out = 4 v rev. 0 | page 7 of 24
ADM7151 data sheet ?40 ?5 25 85 125 shutdown current (a) temperature (c) 10 1 0.1 0.01 0.001 0.0001 v in = 6.2v v in = 6.5v v in = 7.0v v in = 10v v in = 16v 1 1480-0 1 1 figure 11 . shutdown current vs. temperature at various input voltages ?40 ?5 25 85 125 v out (v) junction temperature (c) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 5.00 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 1 1480-012 figure 12 . output voltage (v out ) vs. junction temperature (t j ), ADM7151 - 04, v out = 5 v 1 10 100 1000 v out (v) i load (ma) 5.00 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 1 1480-013 figure 13 . output voltage (v out ) vs. load current (i load ), ADM7151 - 04, v out = 5 v v out (v) v in (v) 16 12 14 10 8 6 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 1 1480-014 figure 14 . output voltage (v out ) vs. input volta ge (v in ), ADM7151 - 04, v out = 5 v ?40 ?5 25 85 125 ground current (ma) junction temperature (c) load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma 10 0 1 2 3 4 5 6 7 8 9 1 1480-015 figure 15 . ground current vs. junction temperature (t j ), ADM7151 - 04 , v out = 5 v 1 10 100 1000 ground current (ma) i load (ma) 10 0 1 2 3 4 5 6 7 8 9 1 1480-016 figure 16 . ground current vs. load current (i load ), ADM7151 - 04, v out = 5 v rev. 0 | page 8 of 24
data sheet ADM7151 11480-017 ground current (ma) v in (v) 16 12 14 10 8 6 0 1 2 3 4 5 6 7 8 9 10 load = 1ma load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 17 . ground current vs. input voltage ( v in ), ADM7151 - 04, v out = 5 v 1 10 100 1000 dropout voltage (ma) i load (ma) 700 0 100 200 300 400 500 600 1 1480-018 figure 18 . dropout voltage vs . load current (i load ), ADM7151 - 04, v out = 5 v 11480-019 v out (v) v in (v) 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.0 5.2 5.0 4.8 4.6 4.4 4.2 v dropout = 5ma v dropout = 10ma v dropout = 100ma v dropout = 200ma v dropout = 400ma v dropout = 800ma figure 19 . output voltage (v out ) vs. input voltage (v in ) in dropout, ADM7151 - 04, v out = 5 v 11480-020 ground current (a) v in (v) 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 0 12 10 8 6 4 2 i gnd = 5ma i gnd = 10ma i gnd = 100ma i gnd = 200ma i gnd = 400ma i gnd = 800ma figure 20 . ground current vs. input v oltage (v in ) in dropout, ADM7151 - 04, v out = 5 v 11480-021 psrr (db) frequency (hz) 10m 1m 100k 10k 1k 100 10 1 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 21 . power supply rejection ratio (psrr) vs. frequency, ADM7151 - 02, v out = 4 v 11480-022 psrr (db) frequency (hz) 10m 1m 100k 10k 1k 100 10 1 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 22 . power supply rejection ratio (psrr) vs. frequency, ADM7151 - 04, v out = 5 v rev. 0 | page 9 of 24
ADM7151 data sheet 11480-023 psrr (db) frequency (hz) 10m 1m 100k 10k 1k 100 10 1 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 600mv 700mv 800mv 900mv 1.0v 1.1v 1.2v 1.3v 1.4v figure 23 . power s upply rejection ratio (psrr) vs. frequency for various headroom voltages , ADM7151 - 02, v out = 4 v, 400 ma load 11480-024 psrr (db) frequency (hz) 10m 1m 100k 10k 1k 100 10 1 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 600mv 700mv 800mv 900mv 1.0v 1.1v 1.2v 1.4v 1.6v 1.8v figure 24 . power supply rejection ratio (psrr) vs. fre quency for various headroom voltages , ADM7151 - 04, v out = 5 v, 400 ma load 11480-025 psrr (db) headroom (v) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 ?120 ?100 ?80 ?60 ?40 ?20 0 100hz 10khz 1mhz 10hz 1khz 100khz 10mhz figure 25 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 02, v out = 4 v, 100 ma load 11480-026 psrr (db) headroom (v) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 26 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 02, v out = 4 v, 400 ma load 11480-027 psrr (db) headroom (v) 1.6 1.4 1.5 1.3 1.2 1.1 1.0 0.9 0.8 0.7 ?120 ?100 ?80 ?60 ?40 ?20 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 27 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 02, v out = 4 v, 800 ma load 11480-028 psrr (db) headroom (v) 1.5 0.3 0.5 0.7 0.9 1.1 1.3 ?140 ?120 ?100 ?60 ?20 ?80 ?40 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 28 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 04, v out = 5 v, 100 ma load rev. 0 | page 10 of 24
data sheet ADM7151 11480-029 psrr (db) headroom (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 ?120 ?100 ?60 ?20 ?80 ?40 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 29 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 04, v out = 5 v, 400 ma load 11480-030 psrr (db) headroom (v) 1.7 1.5 1.3 1.1 0.9 0.7 ?120 ?100 ?60 ?20 ?80 ?40 0 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz figure 30 . power supply rejection ratio (psrr) vs. headroom voltage, ADM7151 - 04, v out = 5 v, 800 ma load 11480-031 noise (vrms) load current (ma) 1000 100 10 0 2.0 1.6 1.2 0.8 0.4 10hz to 100khz figure 31 . rms output noise vs. load current (i load ), 10 hz to 100 k hz, ADM7151 - 04, v out = 5 v 11480-032 noise (vrms) load current (ma) 1000 100 10 0 2.0 1.6 1.2 0.8 0.4 100hz to 100khz figure 32 . rms output noise vs. load current (i load ), 100 hz to 100 k hz, ADM7151 - 04, v out = 5 v 11480-033 noise (vrms) load current (ma) 1000 100 10 0 2.0 1.6 1.2 0.8 0.4 10hz to 100khz figure 33 . rms output noise vs. load current (i load ), 10 hz to 100 k h z, ADM7151 - 02, v out = 4 v 11480-034 noise (vrms) load current (ma) 1000 100 10 0 2.0 1.6 1.2 0.8 0.4 100hz to 100khz figure 34 . rms output noise vs. load current (i load ), 1 00 hz to 100 k hz, adm 7151 - 02, v out = 4 v rev. 0 | page 11 of 24
ADM7151 data sheet 11480-035 noise spectral density (nv/hz) frequency (hz) 10m 100k 1m 10k 1k 0.1 10 1 figure 35 . output noise spectral density, 1 k hz to 10 mhz, i load = 10 ma 11480-036 noise spectral density (nv/hz) frequency (hz) 100k 10k 1k 100 10 1 0.1 1 10 100 1k 100k 10k figure 36 . output noise spectral density, 0.1 hz to 10 k hz, i load = 10 ma 11480-037 noise spectral density (nv/hz) frequency (hz) 10m 1m 100k 10k 1k 100 10 0.1 1 10 100 1k load = 800ma load = 400ma load = 200ma load = 100ma load = 10ma figure 37 . output noise spectral density at different load current s, 10 hz to 10 mhz 11480-038 noise spectral density (nv/hz) frequency (hz) 1m 100k 10k 1k 100 10 1 0.1 1 10 100 1k 100k 10k load = 10ma load = 100ma load = 200ma load = 400ma load = 800ma figure 38 . output noise spectral density at different load currents, 0.1 hz to 1 mhz 11480-039 noise spectral density (nv/hz) frequency (hz) 1m 100k 10k 1k 100 10 1 0.1 1 10 100 1k 100k 10k c byp = 1f c byp = 4.7f c byp = 10f c byp = 22f c byp = 47f c byp = 100f c byp = 470f c byp = 1mf figure 39 . output noise s pectral density vs . at different c byp , load current = 10 ma ch1 500ma b w ch2 20mv b w m20s a ch1 200ma t 10.40% 1 2 t 1 1480-040 figure 40 . load transient response, i load = 1 ma to 800 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out rev. 0 | page 12 of 2 4
data sheet ADM7151 ch1 500ma b w ch2 10mv b w m4s a ch1 200ma t 11.0% 1 2 t 1 1480-041 figure 41 . load transient r esponse, i load = 10 ma to 800 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 200ma b w ch2 10mv b w m2s a ch1 460ma t 11.0% 1 2 t 1 1480-042 figure 42 . load transient response, i load = 100 ma to 600 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 50.0ma b w ch2 2.0mv b w m4s a ch1 50.0ma t 10.0% 1 2 t 1 1480-043 figure 43 . load transient response, i load = 1 ma to 100 ma, v out = 5 v, v in = 6.2 v , ch1 = i out , ch2 = v out ch1 1.0v b w ch2 2.0mv b w m10s a ch1 1.14v t 10.0% 1 2 t 1 1480-044 figure 44 . line transient response, 2 v input step, i load = 800 ma, v out = 1.8 v, v in = 4.5 v , ch1 = v in , ch2 = v out ch1 1.0v b w ch2 2.0mv b w m10s a ch3 1.14v t 10.0% 1 2 t 1 1480-045 figure 45 . line transient response, 2 v input step, i load = 800 ma, v out = 3.3 v, v in = 4.5 v , ch1 = v in , ch2 = v out ch1 1.0v b w ch2 2.0mv b w m10s a ch3 1.14v t 10.0% 1 2 t 1 1480-046 figure 46 . line transient response, 2 v input step, i load = 800 ma, v out = 5 v, v in = 6.2 v , ch1 = v in , ch2 = v out rev. 0 | page 13 of 24
ADM7151 data sheet volts time (ms) 10 0 1 2 3 4 5 6 7 8 9 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v en v reg v ref v out 1 1480-047 figure 47 . v out , v ref , v reg start - up time s a fter v en rising , v out = 3.3 v, v in = 5 v rev. 0 | page 14 of 24
data sheet ADM7151 theory of operation the ADM7151 is a n adjustable , ultra low noise, high power supply rejection ratio (psrr) linear regulator targeting radio frequency (rf) applications. the input voltage range is 4.5 v to 16 v , and it can deliver up to 8 00 ma of output current. typical shutdown current consum ption is 0. 1 a at room temperature. optimized for use with 1 0 f ceramic capacitors, the ADM7151 provides excellent transient performance. vreg gnd vout vin en ref ref_sense reference shutdown active ripple filter short circuit, thermal protect ota e/a byp 1 1480-048 figure 48 . adjustable ou tput voltage internal block diagram internally, the ADM7151 consists of a reference, an error amplifier , a feedback voltage divider, and a p - channel mos fet pass transistor. output current is de livered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference vol tage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass an d decreasing the output voltage. by heavily filtering the reference voltage, the ADM7151 is able to achieve 1.7 nv/hz output typical from 10 khz to 1 mhz . because the error amplifier is always in unity gain, the output noise is independent of the output voltage. to maintain very high psrr over a wide frequency range, the ADM7151 architecture uses an internal active ripple filter . this stage isolates the low output noise ldo from noise on vin. the result is that the ADM7151 psrr is signifi cantly higher over a wider frequency range than any single stage ldo. the ADM7151 output voltage can be adjusted between 1.5 v and 5.1 v and is available in two models that optimize the input v oltage and output voltage ranges to keep power dissipation as low as possible without compromising psrr performance. the output voltage is determined by an external voltage divider according to the following equation: v out = 1.5 v ( 1 + r1 / r2 ) vout ref ref_sense gnd vin en byp vreg v byp v reg ADM7151-04 c reg 10f c byp 1f c ref 1f v out = 1.5v (r1 + r2)/r2 1k < r2 < 200k c in 10f c out 10f off on v in = 6.2v v out = 5.0v r1 r2 1 1480-049 figure 49 . typical adjustable output voltage application schematic the r2 value must be greater than 1 k to prevent excessive loading of the reference voltage appearing on the ref pin. to minimize errors in the output voltage caused by the ref_sense pin input current , the r2 value must be less than 200 k . for example, when r1 and r2 each equal 200 k, the output voltage is 3.0 v. the output voltage error introduced by the ref_sense pin input current is 10 mv or 0. 33 %, assuming a maximum ref_sense pin input current of 10 0 na at 1 25c. the ADM7151 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on, and when en is low, vout turns off . for automatic startup, en can be tied to vin. vreg vin ref_sense ref out byp gnd en 18v 6v 6v 6v 6v 6v 6v 6v 6v 18v 18v 1 1480-050 figure 50 . simplified esd protection block diagram the esd protection devices are shown in the block diagram as zener diodes (see figure 50). rev. 0 | page 15 of 24
ADM7151 data sheet applications information model selection t he ADM7151 is available in two models to allow the user to select the best combination of power dissipation and psrr performance for a given application. capacitor selection output capacitor the ADM7151 is desi gned for operation with ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor af fects the stability of the ldo control loop. a minimum of 10 f capacitance with an esr of 0.2 ? or less is recommended to ensure the stability of the ADM7151 . output capacitance also affects t ransient response to changes in load current. using a larger value of output capacitance improves the transient response of the ADM7151 to large changes in load current. figure 51 shows the transient responses for an output capacitance value of 10 f. ch1 500ma b w ch2 10mv b w m4s a ch1 200ma t 11.0% 1 2 t 1 1480-051 figure 51 . output transient response, v out = 5 v, c out = 10 f input and vreg capacitor connecting a 10 f capacitor from vin t o gnd reduces the circuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. to maintain the best possible stability and psrr performance, connect a 10 f capacitor from vreg to gnd. when more than 10 f of output capacitance is required, increase the input and vreg capacitors to match it. ref capacitor the ref capacitor is necessary to stabilize the reference amplifier . connect a capacitor of a t least 1 f between ref and gnd. table 6 . model selection guide for psrr model v out range (v) psrr (db) at 800 ma, 1.2 v headroom psrr (db) at 400 ma, 1 v headroom 10 khz 100 khz 1 mhz 10 khz 100 khz 1 mhz ADM7151 - 02 1. 5 to 4.0 91 91 50 94 94 58 ADM7151 - 04 1.5 to 5.1 84 84 53 94 94 67 table 7 . model selection guide for input voltage model v out range (v) minimum v in at 800 ma load mi nimum v in at 400 ma load v out < 3.3 v v out < 5 v v out 3.3 v v out 5 v v out < 3.3 v v out < 5 v v out 3.3 v v out 5 v ADM7151 - 02 1.5 to 4.0 4.5 v n/a 1 v out + 1.2 v n/a 1 4.5 v n/a 1 v out + 1.0 v n/a 1 ADM7151 - 04 1.5 to 5.1 n/a 1 6.2 v n/a 1 v out + 1.2 v n/a 1 6 v n/a 1 v out + 1.0 v 1 n/a = not applicable. rev. 0 | page 16 of 24
data sheet ADM7151 byp capacitor the byp capacitor is necessary to filter the reference buffer. a 1 f capacitor is typically connected between byp and gnd. capacitors as small as 0.1 f can be used ; however, the output noise voltage of the ldo increase s as a result. in addition, t he byp capacitor can be increased to reduce the noise below 1 k hz at th e expense of increasing the start - up time of the ldo. very large values of c byp significantly reduce the noise below 10 h z. tantalum capacitors are recommended for capacitors larger than about 33 f. a 1 f ceramic capacitor in parallel with the larger tan talum capacitor is required to retain good noise performance at higher frequencies. noise spectral density (nv/hz) frequency (hz) 1m 0.1 1 10 100 1k 10k 100k 1 100k 100 1k 10k 10 c byp = 1f c byp = 4.7f c byp = 10f c byp = 22f c byp = 47f c byp = 100f c byp = 470f c byp = 1mf 1 1480-052 figure 52 . noise spectral density vs. frequency, c byp = 1 f to 1 mf noise spectral density (nv/hz) c byp (f) 1000 1 10 100 1 10k 100 1k 10 1hz 10hz 100hz 400hz 3hz 30hz 300hz 1khz 1 1480-053 figure 53 . noise spectral density vs. c byp for di fferent frequencies capacitor properties any good quality ceramic capacitors can be used with the ADM7151 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capa citors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditio ns. x5r or x7r dielectrics with a voltage rating of 6.3 v to 50 v are recommended. however, y5v and z5u dielectrics are not recommended due to their poor temperature and dc bias characteristics. figure 54 depic ts the capacitance vs. dc bias voltage of a 1206, 10 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rati ng. in general, a capacitor in a larger package or higher voltage rating exhibit s better stability. the temperature variation of the x5r dielectric is ~ 15% over the ?40c to +85c temperature range and is not a function of package or voltage rating. capacitance (f) dc bias voltage (v) 10 0 4 8 2 6 0 12 10 8 6 4 2 1 1480-054 figure 54 . capacitance vs. dc bias voltage use equation 1 to determine the worst - case capacitance accoun ting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the wo rst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco ) over ? 4 0c to +85c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 9.72 f at 5 v, as shown in figure 54. substituting these values in equation 1 yields c eff = 9.72 f (1 ? 0.15) (1 ? 0.1) = 7.44 f therefore, the capacitor chosen in this examp le meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the ADM7151 , it is imperative that the effec ts of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. rev. 0 | page 17 of 24
ADM7151 data sheet enable (en) and undervoltage loc kout (uvlo) the ADM7151 uses the en pin to en able and disable the vout pin under normal operating conditions. as shown in figure 55, when a rising voltage on en crosses the upper threshold, vout turns on. when a falling voltage on en crosses the lower threshold, vout turns off. the hysteresis varies as a function of the input voltage. for example, the en hysteresis is approximately 200 mv with an input voltage of 4.5 v. v out (v) v en (v) 1.6 1.5 1.0 1.2 1.4 1.1 1.3 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 vout_en_rise vout_en_fall 1 1480-055 figure 55 . typical v out response to en pin operation , v out = 3.3 v, v in = 5 v en rise threshold (v) v in (v) 16 +125c +25c ?40c 14 12 10 8 6 1.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1 1480-056 figure 56 . typical en ris e threshold vs . input voltage (v in ) for various temperature s en fall threshold (v) v in (v) 16 +125c +25c ?40c 14 12 10 8 6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1 1480-057 figure 57 . typical en fall threshold vs . input voltage (v in ) for various temperatures the ADM7151 also incorporates an internal undervoltage lockout circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. the upper and lower thre sholds are internally fixed with approximately 300 mv of hysteresis. v out (v) v in (v) 4.5 4.4 4.0 4.2 4.3 4.1 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 vout_vin_rise vout_vin_fall 1 1480-058 figure 58 . typical uvlo hysteresis , v out = 3.3 v figure 58 shows the typical hysteresis of the uvlo function. this hy steresis prevents on/off oscillations that can occur due to noise on the input voltage as it passes through the threshold points. rev. 0 | page 18 of 24
data sheet ADM7151 start - up time the ADM7151 uses an internal soft start to limit the inrush current when the output is enabled. the start - up time for a 5 v output is approximately 3 ms from the time the en active threshold is crossed to when the output reaches 90% of its final value. the rise time of the output voltage (10% to 90%) is approximately 0.0012 c byp s econds where c byp is in microfarads. v out (v) time (seconds) 0.020 0.016 0 0.008 0.012 0.004 0.018 0.014 0.006 0.010 0.002 0 6 5 4 3 2 1 enable c byp = 1f c byp = 4.7f c byp = 10f 1 1480-059 figure 59 . typical start - up behavior with c byp = 1 f to 10 f v out (v) time (seconds) 0.20 0.16 0 0.08 0.12 0.04 0.18 0.14 0.06 0.10 0.02 0 6 5 4 3 2 1 enable c byp = 10f c byp = 47f c byp = 330f 1 1480-060 figure 60 . typical start - up behavior with c byp = 10 f to 330 f ref , byp, and vreg p ins ref, byp, and vreg are internally generated voltages that require external bypass capacitors for proper operation. do not , under any circumstances , connect any loads to these pins because d oing so compromise s the noise and psrr pe rformance of the ADM7151 . using larger values of c byp , c ref , and c reg is acceptable but can increase the start - up time , as described in the start - up time section. curr ent - limit and thermal ov erload protection the ADM7151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the ADM7151 is designed to current limit when the output load reaches 1 .3 a (typical). when the output load exceeds 1 .3 a, the output voltage is reduced to maintain a constant current limit. thermal overload protect ion is included, which limits the junction temperature to a maximum of 155c (typical). under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 155c, the output is turne d off, reducing the output current to zero. when the junction temperature drops below 140c, the output is turned on again, and output current is restored to its operating value. consider the case where a hard short from vout to gnd occurs . at first, the ADM7151 current limits, so that only 1 . 3 a is conducted into the short. if self heating of the junction is great enough to cause its temperature to rise above 155c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 140c, the output turns on and conducts 1 . 3 a into the short, again causing the junction temperature to rise above 155c. this thermal oscilla tion between 140c and 155c causes a current oscillation between 1 .3 a and 0 ma that continues as long as the short remains at the output. current - limit and thermal limit protections are intended to protect the device against accidental overload conditio ns. for reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 15 0 c. thermal consideratio ns in applications with low input to output voltage differential, the ADM7151 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package can become large enough that it causes the junction temperature of t he die to exceed the maximum junction temperature of 15 0 c. when the junction temperature exceeds 155c, the converter enters thermal shutdown. it recovers only after the junction temperat ure decrease s below 140c to prevent any permanent damage. therefor e, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions . the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to t he power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the ADM7151 must not exceed 15 0 c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pin and exposed pad to the pcb. rev. 0 | page 19 of 24
ADM7151 data sheet table 8 shows typical ja values of the 8 - l ead soic and 8 - lead lfcsp packages for various pcb copper sizes. table 9 shows the typical jb values of the 8 - lead soic and 8 - lead lfcsp. table 8 . typical ja values ja (c/w) copper size (mm 2 ) 8 - lead lfcsp 8 - lead soic 25 1 165.1 165 100 125.8 126.4 500 68.1 69.8 1000 56.4 57.8 6400 42.1 43.6 1 device soldered to minimum size pin traces. table 9 . typical jb values package jb (c/w) 8 - lead lfcsp 15.1 8 - lead soic 17.9 th e junction temperature of the ADM7151 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: v in and v out are th input and output voltages, respectively. i load is the load current. i gnd is the groun e d current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 15 0 c. the heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADM7151 . adding thermal planes under the package also improves thermal performance. however, as listed in table 8 , a point of diminishing returns is eventually reached, b eyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance. figure 61 to figure 66 show junction temp erature calculations for different ambient temperatures, power dissipation, and areas of pcb copper. 1 1480-061 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 25 35 45 55 65 75 85 95 105 115 125 135 145 155 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 figure 61 . junction temperature vs. total power dissipation for the 8 - lead lfcsp, t a = 25c 11480-062 junction temperature (c) total power dissipation (w) 1.8 2.0 2.2 2.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 60 70 80 90 100 110 120 140 160 130 150 6400mm 2 500mm 2 25mm 2 t j max figure 62 . junction temperature vs. total power dissipation for the 8 - lead lfcsp, t a = 50c 1 1480-063 junction temperature (c) total power dissipation (w) 1.5 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 65 75 85 95 105 115 125 135 155 145 6400mm 2 500mm 2 25mm 2 t j max figure 63 . junction temperature vs. total power dissipation for the 8 - lead lfcsp, t a = 85c rev. 0 | page 20 of 24
data sheet ADM7151 1 1480-064 junction temperature (c) total power dissipation (w) 2.8 2.6 2.4 3.0 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 155 145 125 102 85 65 45 135 115 95 75 55 35 6400mm 2 500mm 2 25mm 2 t j max figure 64 . junction temp erature vs. total power dissipation for the 8 - lead soic, t a = 25c 11480-065 junction temperature (c) total power dissipation (w) 1.8 2.0 2.2 2.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 50 60 70 80 90 100 110 120 130 160 150 140 6400mm 2 500mm 2 25mm 2 t j max figure 65 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 50c 1 1480-066 junction temperature (c) total power dissipation (w) 2.0 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 65 75 85 95 105 115 125 135 155 145 6400mm 2 500mm 2 25mm 2 t j max figure 66 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 85c thermal characterization parameter ( jb ) when the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise ( see figure 67 and figure 68 ). maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical value of jb is 15.1c/w for the 8 - lead lfcsp package and 17.9c/w for the 8 - lead soic package. 1 1480-067 junction temperature (c) total power dissipation (w) 9.0 8.5 8.0 7.0 6.0 7.5 6.5 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 160 140 120 100 80 60 40 20 t b = 25c t b = 50c t b = 65c t b = 85c t j max figure 67 . junction temperature vs. total power dissipation for the 8 - lead lfcsp 1 1480-068 junction temperature (c) total power dissipation (w) 5.5 7.5 7.0 6.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 160 140 120 100 80 60 40 20 t b = 25c t b = 50c t b = 65c t b = 85c t j max figure 68 . junction temperature vs. total power dissipation for the 8 - lead soic rev. 0 | page 21 of 24
ADM7151 data sheet printed circuit boar d layout considerations place the input capacitor as close as possible to the vin and gnd pins. place the output capacitor as close as possible to the vout and gnd pins. place t he bypass capacitors for v reg , v ref , and v byp close to the respective pins and gnd. use of an 0805, 0603, or 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited. 1 1480-069 figure 69 . example 8 - lead lfcsp pcb layout 1 1480-070 figure 70 . example 8- lead soic pcb layout rev. 0 | page 22 of 24
data sheet ADM7151 outline dimensions 2.44 2.34 2.24 t o p view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a se a ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 1 1-28-2012-c 0.20 min figure 71 . 8- lead lead frame chip scale package [lfcsp _wd ] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 11 ) dimensions shown in millimeters compliant t o jedec s t andards ms-012-a a 06-03-20 1 1-b 1.27 0.40 1.75 1.35 2.41 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc sea ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 3.098 figure 72 . 8 - lead standard small outline package, with exposed pad [soic_n_ep] narrow body (rd - 8- 2) dimensions shown in millimeters rev. 0 | page 23 of 24
ADM7151 data sheet ordering guide model 1 temperat ure range output voltage range (v ) package description package option branding ADM7151acpz -02- r2 ?40c to +125c 1.5 to 4.0 8 - lead lfcsp_wd cp -8 -11 lnn ADM7151acpz -02- r7 ?40c to +125c 1.5 to 4.0 8 - lead lfcsp_wd cp -8 -11 lnn ADM7151ardz -02 ?40c to +125 c 1.5 to 4.0 8 - lead soic_n_ep rd -8 -2 ADM7151ardz -02 -r7 ?40c to +125c 1.5 to 4.0 8 - lead soic_n_ep rd -8 -2 ADM7151cp -02- evalz 1.5 to 4.0 evaluation board ADM7151acpz -04- r2 ?40c to +125c 1.5 to 5.1 8 - lead lfcsp_wd cp -8 -11 lnp ADM7151acpz -04- r 7 ?40c to +125c 1.5 to 5.1 8 - lead lfcsp_wd cp -8 -11 lnp ADM7151ardz -04 ?40c to +125c 1.5 to 5.1 8 - lead soic_n_ep rd -8 -2 ADM7151ardz -04 -r7 ?40c to +125c 1.5 to 5.1 8 - lead soic_n_ep rd -8 -2 1 z = rohs compliant part. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11480 - 0 - 9/13(0) rev. 0 | page 24 of 24

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